Remember all those days looking at a small screen following the tiny cubes falling down quicker and quicker…? Never again! Those days are gone and for good. We are not saying that you no longer have to play Tetris, just that you don´t have to do it on a small screen.
Today´s tutorial will teach you how to build your own Giant Tetris. You read it right, giant. The one used in the article is 6 ft tall, but you can adapt it to your needs…or just to the height of your ceiling.
All you need is a grid of RGB LEDs and a Papilio FPGA board, follow each step of this thorough tutorial and build your own Giant Tetris!
Here is a promising looking Soft Processor core available on OpenCores.com. It looks like it has some nice simulation and debugging tools built in – as well as a C toolchain.
Included with the package is oldland-rtlsim, which lets you simulate the processor on a PC. The oldland-debug tool lets you connect to the processor for programming and debugging over JTAG. Finally, there’s a GNU toolchain port that lets you build C code for the device.
Pyroedu has posted a video course on FPGA’s. Since it based on Altera FPGA some of the portions are not 100% applicable, but there is a bunch of good basic FPGA info in the lessons. It makes a nice addition to hamster intro to FPGA document, especially for those who learn better from watching a video over reading. Hope it helps someone out.
Here is a nice technical write-up of the OV7670 camera module that can be purchased on eBay for under $10. We have a Wing that lets you easily connect this camera to the Papilio. There are also VHDL code examples out there on Hamster’s Wiki page. All we need now is to make a DesignLab library for these puppies!
The OV7670 is a low cost image sensor + DSP that can operate at a maximum of 30 fps and 640 x 480 (“VGA”) resolutions, equivalent to 0.3 Megapixels. The captured image can be pre-processed by the DSP before sending it out. This preprocessing can be configured via the Serial Camera Control Bus (SCCB). You can see the full datasheet here.
Excellent method to infer a Block RAM memory block of any size in simple code that works for Xilinx and Altera devices. I needed to generate some BRAM for a DesignLab module I was putting together and I remembered I had seen this somewhere but couldn’t remember where… Some digging in google brought this back up so I thought I better get this posted to the blog so we can easily find it in the future.
I’m a big fan of inference, especially as it applies to writing synthesizable Verilog code for FPGAs. Properly coded, a module that infers technology-dependent blocks (e.g. block RAMs) should: be portable between devices from a particular vendor (e.g. Spartan 3E to Virtex 6), be portable between devices from different vendors (e.g. Spartan 6 to Cyclone III), and even be portable to vendor-independent environments (e.g. simulation in Icarus Verilog).
Exciting news! We just hit a major milestone with a DesignLab 0.2.0 release for both Windows and Linux that can be downloaded here. This is the first release that has all of the core functionality envisioned for DesignLab in place:
- -Every sketch has an FPGA circuit associated with it and there is smooth integration between the sketch interface and the Xilinx schematic editor.
- -No longer any need to jump through hoops to configure Xilinx ISE to work with DesignLab. As long as you have Xilinx ISE Webpack installed DesignLab will take care of the rest.
- -Logic Analyzer functionality is working under Windows and Linux.
- -The ZPUino Soft Processor has been updated to 2.0 with exciting new features like automatic discovery of what peripherals are connected to Wishbone slots.
- -Flex pins allow you to connect the output from any chip to a pin that can be moved on the fly to any physical pin on the Papilio DUO board. For example, a single line of code allows you to move the output of a UART to any of the 54 available pins.
- -DesignLab Libraries are very ease to create and share now. Put all of the Schematic symbols, VHDL, working circuits, and example C code in one library directory and DesignLab takes care of including it in all the right places.
- -DesignLab Libraries have been greatly expanded to include C++ code, Xilinx Schematic Symbols, VHDL, Verilog, EDIF, and NGC files.
There are countless other improvements and changes, this release is basically all of the things that I’ve been thinking about for the last year finally implemented! It should be everything we need to create and share useful FPGA circuits without learning a new programming language like VHDL or Verilog.
Of course, just like the Arduino IDE is only as good as the libraries that can downloaded to provide new functionality we have a lot of work to do to provide exciting and useful FPGA libraries for DesignLab. This 0.2.0 release was focused on the functionality we needed to implement the idea of integrating FPGA circuits with sketches. Now that we have the framework in place it is time to start on the fun part of building on that framework with exciting and useful libraries that provide chips/cores to use in your circuit designs. While we have a good start with the ZPUino Soft Processor libraries, Benchy debugging libraries, and ZPUino Wishbone libraries we have the following new libraries in mind to work on:
- Gameduino VGA Chip – Will allow you to add VGA output to any of your circuits using the well documented and Open Source VGA chip/core from James Bowman.
- BitCoin Miner Chip – Why not mine some bitcoins while your Papilio DUO is not in use?
- High Speed Xilinx UART Chip – A standalone UART chip/core that is able to pump speeds up to 3Mb/s through the FTDI USB chip. This is not a wishbone chip so you can use it by itself in any of your projects.
- RGB Panel Driver Chip – Drive a RGB panel like Alvaro did in his demo for the Papilio DUO.
- Pacman Chip – Turn the Pacman motherboard into a single chip that you can drop into any of your circuits. Make a custom Pacman ROM with MAME and then have it run on actual Pacman hardware in one of your circuits. Maybe use the Pacman hardware for graphics and a Commodore SID chip for audio…
These are just a few ideas for some of the low hanging fruit that should be easy to implement. I’m hoping with the release of DesignLab we will see the Papilio community start releasing libraries that we can all use and enjoy in our custom FPGA circuits.
I’m setting a goal of releasing one library a week, once the Papilio DUO is delivered and in everyone’s hands I will put all of those libraries together into the first DesignLab 1.0 release.
So that comes to the question that I know must be burning in everyone’s mind. When will the Papilio DUO hardware be delivered? After all it is December now, the target date for the hardware release…
I was hoping to write this update with a double dose of good news about the DesignLab release and a solid delivery date for the hardware. The good news is that Seeed Studio has finished manufacturing all of the Papilio DUO boards. But the bad news is that we have run into a temporary snag with testing the boards. The part of the test plan that I wrote to program the Arduino bootloader on the ATmega32u4 chip is failing on a small amount of boards… We have tried to figure out what is happening online but with the time zone differences and language barrier it has proven to be too difficult. Seeed shipped out a batch of failing boards to me on Friday so I can get to the bottom of what is happening. I don’t expect this to be a big deal, it is probably just a minor configuration change in the software or something, but unfortunately it makes it impossible to give a solid delivery date. Once I have a solution and Seeed can get back on track with testing the boards we will be better able to give a more accurate delivery date. I’m hoping everything goes smooth from here on out and we can start shipping before Christmas. As soon as I figure this out I’ll post an update. Thank you for your patience and we will do everything we can to deliver in December.
Papilio One spotted in article about Open Source Hardware!
Developments in open source are not just exciting as viable and marketable options, but as a real boon for innovation. Growing interest along with shared goals to create and better developments in science and technology inspired a team at CERN to create the Open Hardware Repository and Open Hardware License. Additionally, open source hardware groups hope to inspire more people from diverse backgrounds to join the innovation.
Here at Gadget Factory we are happy to announce that our next generation of products are now available at our online store. The long awaited Papilio DUO along with the new Papilio Shields are finally here after a successful Kickstarter campaign that helped us raise more than $62,000 in funds to make this dream come true, here is a short description of each product:
- The Papilio DUO has an FPGA on the top and the same chip that is used in the Arduino Leonardo (ATmega32U4) on the bottom. It’s like having an Arduino with a full circuit laboratory connected to it! For example, you can draw circuits to move pins, connect extra serial ports, or connect a bitcoin miner to the Arduino-Compatible chip. Just plug it into your computer using a USB cable, download our software and start drawing your own circuits.
To have an in depth look at the DUO please visit the hardware guides and the Papilio DUO product page here, feel free to drop a comment and send us your feedback.
Making an Open Source Hardware device and need a USB VID/PID but can’t afford $5K? Well now there is a new option for getting your own PID for free!
Now, someone has finally done the sensible thing and put an unused USB VID to work. pid.codes obtained the rights to a single VID – 0x1209 – and now they’re parceling off all the PIDs that remain to open source hardware projects.