Inferring true dual-port, dual-clock RAMs in Xilinx and Altera FPGAs

Excellent method to infer a Block RAM memory block of any size in simple code that works for Xilinx and Altera devices. I needed to generate some BRAM for a DesignLab module I was putting together and I remembered I had seen this somewhere but couldn’t remember where… Some digging in google brought this back up so I thought I better get this posted to the blog so we can easily find it in the future.

I’m a big fan of inference, especially as it applies to writing synthesizable Verilog code for FPGAs. Properly coded, a module that infers technology-dependent blocks (e.g. block RAMs) should: be portable between devices from a particular vendor (e.g. Spartan 3E to Virtex 6), be portable between devices from different vendors (e.g. Spartan 6 to Cyclone III), and even be portable to vendor-independent environments (e.g. simulation in Icarus Verilog).


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